1. Technical Field
The present invention relates to a semiconductor integrated circuit device, and, in particular, to a CMOS master-slice-type semiconductor integrated circuit device capable of extending the degree of design freedom available, thereby bringing about the advantages of higher integration and efficiency and of further improvement of the tolerance with respect to the latch-up phenomenon.
2. Prior Art
FIG. 1 shows a conventional basic cell as disclosed in Japanese Patent Public Disclosure No. 74647/85. In this figure, basic cell 100 comprises two gate electrodes 101, p.sup.+ -type source/drain regions 102, n.sup.+ -type contact diffusion regions of the substrate 103, p.sup.+ -type contact diffusion regions of the p-well 104 and n.sup.+ -type source/drain regions 105. Thus, a p-type MOS transistor 106 and an n-type MOS transistor 107 are formed.
In such a basic cell, n.sup.+ -type contact diffusion regions of the substrate 103 and p.sup.+ -type contact diffusion regions of the p-well 104 are disposed between a pair of transistors consisting of p-type MOS transistor 106 and n-type MOS transistor 107. The purpose of this is to heighten the substrate potential and the well potential, and to improve the tolerance with respect to the latch-up phenomenon which occurs between p-type MOS transistor 106 and n-type MOS transistor 107. By interconnecting the gate electrodes of p-type transistor 106 and the gate electrodes of n-type transistor 107, the size of basic cell 100 can be reduced and the degree of integration can be improved.
Accordingly, in a gate array in which such basic cells are arranged regularly so as to form a plurality of rows of basic cells, if a sufficient distance is maintained between the adjacent rows, no particular problem is caused so long as the respective basic cells include n.sup.+ -type contact diffusion regions 103 and p.sup.+ -type contact diffusion regions 104 disposed between MOS transistors 106 and 107 of a different conductivity type.
Consideration should now be given to gate arrays having a plurality of rows of basic cells disposed at shorter intervals from each other and structured as described above. Some examples of such gate arrays are a gate array having narrow wiring regions and a small number of gates, and a gate array having the rows of basic cells arranged in close proximity to each other (hereinafter, called "a pavement-type gate array"). In the adjacent two rows of basic cells in such gate arrays, the contact diffusion regions of the substrate and the contact diffused regions of the p-well are not provided between the p-type MOS transistors in one of the rows of basic cells and the n-type MOS transistors in the other row of basic cells, that is, in the CMOS structure formed by these two different type transistors, and this leads to the possibility of the latch-up phenomenon occurring in the regions of the CMOS structure. The pavement-type gate arrays also involve the problem of necessitating variations in the wiring channel regions in accordance with the length of the longer side of one basic cell.